XRT72L71 Datasheet | Exar

SCRIPTION The XRT72L71 DS3 ATM User Network Interface (UNI)/Clear-Channel Framer is designed to function as either a DS3 ATM UNI or Clear channel framer. For ATM UNI applications, this device provides the ATM Physical Layer (Physical Medium Dependent and Transmission Convergence sub-layers) interface for both the public and private networks at DS3 rates. For Clear-Channel framer applications, this device supports the transmission and reception of “user data” via the DS3 payload bits. The XRT72L71incorporates Receive, Transmit, Microprocessor Interface, Performance Monitor, Test and Diagnostic and Line Interface Unit Scan Drive sections. APPLICATIONS - Private User Network Interfaces - ATM Switches - ATM Concentrators - DSLAM Equipment - DS3 Frame Relay Equipment Features - pliant with UTOPIA Level 1 and 2 with 8 or 16 Bit Interface Specification and supports UTOPIA Bus speeds of up to 50 MHz - Contains on-chip 16 cell FIFO in both the Transmit (Tx FIFO) and Receive Directions (Rx FIFO) - Contains on-chip 54 byte Transmit OAM Cell buffer and a 108 byte Receive OAM cell buffer, for transmission, reception and processing of OAM cells. - Supports PLCP or ATM Direct Mapping modes - Supports M13 and C-Bit Parity Framing Formats - Supports DS3 Clear Channel Framing Applications - Includes PRBS Generator and Receiver - Supports Local, Remote-Line, Cell, and PLCP Loop-backs - Interfaces to 8 or 16 Bit wide Motorola and Intel µPs - Low power 3.3V, 5V input tolerant, CMOS - 160 pin PQFP Package - 3 and 4 Channel Version also Available FIGURE 1. XRT72L71 SIMPLIFIED BLOCK DIAGRAM WITH SYSTEM INTERFACES UTOPIA BUS Level 1 or 2 Tx UClav XRT72L71 XRT73L00 Tx UTOPIA Interface Tx Cell Processor Tx PLCP Processor Tx DS3 Framer ATM Layer Processor 16 Address 5 Tx POS Tx NEG TCK DMO RLOS RLOL LLOOP RLOOP TAOS Tx LEV Enco Dis Req TPDATA TNDATA TCK DMO RLOS RLOL LLB RLB TAOS Tx LEV ENCODIS Re QDIS RPOS RNEG...